1. Field of the Invention
The present invention relates to a method for manufacturing in a monolithic circuit a through via and an inductance. More specifically, it relates to an inductance of the type described in unpublished French patent application no. 01/13055 filed by the applicant on Oct. 10, 2001, which is incorporated herein by reference.
2. Discussion of the Related Art
The applicant has described in unpublished French patent application no01/15307 filed on Nov. 27, 2001, which is incorporated herein by reference, a two-faced monolithic circuit associating active and passive components. Through vias enable establishing connections between the front surface and the rear surface.
FIGS. 1A and 1B show a cross-section view and a top view of the inductance of French patent application no01/13055. Inductance 10 is formed from a trench etched in a substrate 11. The trench is conventionally obtained by anisotropic etching (for example, a plasma etching) which exposes a portion of substrate 11 according to a pattern of the type of that in FIG. 1B. The trench is insulated from substrate 11 by a conformal insulating layer 12, for example, a silicon oxide layer. The trench is then filled with a conductive material 15 forming inductance 10. The inductance has the shape of a spiral (circular or not) exhibiting first and second ends 16 and 17, first end 16 being substantially located at the center of the spiral.
When an inductance of the above type desired to a formed in a monolithic circuit comprised of one or several vias (not shown) crossing silicon substrate 11 to transfer contacts from one surface to the other, the number of manufacturing steps must be increased. Indeed, the size differences between the etchings necessary to the forming of inductance 10 and of vias (not shown) make it impossible to perform these etchings at the same time. Further, with usual etching processes using an etch mask, it is necessary to complete one of the two structures (inductance or via) before being able to etch the other structure. The holes or trenches formed must indeed be filled up to redeposit an etch mask of definition of the other structure.
The fact of having to form the two structures separately results in that only a single one of them can benefit from the advantages of having its conductive material insulated from the substrate by a thermal oxide formed at high temperature (on the order of 1000xc2x0 C.). Indeed, if a second anneal step was carried out while one of the structures is completed, the high temperatures necessary would deteriorate this first structure.
The present invention aims at the forming of at least one inductance and of at least one through via in a monolithic circuit with common formation steps.
The present invention particularly aims at making the step of forming an insulating layer on the respective walls of the inductance trench and of the through holes of the vias common.
The present invention also aims at enabling formation of this insulating layer for coating the trenches and the vias with a same thermal oxide.
The present invention also aims at providing an inductance and via forming method in a monolithic circuit, which reduces or minimizes the number of manufacturing steps.
To achieve these and other objects, the present invention provides a method for manufacturing, in a monolithic circuit comprising a substrate, an inductance and a through via, in which is formed, from a first surface of the substrate, at least one trench according to the contour of the inductance to be formed; including the steps of forming, by laser in the substrate, a through hole at the location desired for the via; simultaneously insulating the surface of the trench and the hole; and depositing a conductive material in the trench and at least on the hole walls.
According to an embodiment of the present invention, the insulation is performed by thermal oxidation.
According to an embodiment of the present invention, the trench is formed by plasma etching.
According to an embodiment of the present invention, the step of deposition of a conductive material in the trench and on the walls of the holes is followed with a step of filling up the hole with an insulating material.
According to an embodiment of the present invention, the method further comprises a step of planarization of both surfaces of the substrate.
According to an embodiment of the present invention, a via is provided above a central end of the trench of the inductance.
The foregoing objects, features, and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.